In a floating-point normalizer for any particular radix the exponent update may be the critical path. Typically a leading zero detect is performed on the fraction portion of the floating point number to determine the shift amount in the same cycle as the normalization. The shift amount is then subtracted from the input exponent to determine the result's exponent. The exponent path through the subtractor is a critical path in these implementations.
Some designs use a leading zero anticipation (LZA) circuit in the prior cycle during a carry propagate addition (e.g., IBM RS/6000). This causes the shift amount to be known early in the normalization cycle which causes the exponent path to be non-critical, so a subtractor can be used. Leading zero anticipation, however, is very expensive in terms of hardware and it only can be used for post-normalization and not pre-normalization. For pre-normalization there is no prior add cycle to produce a shift amount, thus requiring an additional cycle to produce the shift amount for pre-normalization in this type of implementation.
An additional problem is the determination of sticky bit information which is needed in implementations which have certain rounding modes such as round to nearest even, round to positive infinity, and round to negative infinity. These rounding modes are necessary for compliance with the IEEE 754 floating-point standard; and thus, the sticky bit calculation is a requirement. The sticky bit calculation is basically the logical OR of all bits after the guard bit of a given operand length. During normalization, the location of the guard bit can be determined and which bits should participate in forming the sticky bit. The problem is that additional cycles of latency are required for implementations where the sticky bit is calculated after the guard bit location is determined, or where hints from prior stages are employed in a manner similar to the LZA for exponent calculation.
There remains, therefore, a need for further improvements in determining the exponent and performing the sticky bit computation during normalization.
Accordingly, an object of the present invention is to provide an improved data processing apparatus and method.
Another object of the present invention is to provide an apparatus and method for floating point arithmetic operations, wholly in conformance with ANSI/IEEE Standard No. 754-1985.
It is a feature of the present invention to provide an improved execution unit for floating point normalization.
It is a further feature of the present invention to provide an apparatus, and method for implementing the apparatus, for calculating the exponent and shifting the fraction in parallel during normalization of a floating point number.
It is another feature of the present invention to provide an apparatus, and method for implementing the apparatus, for determining the sticky bit and shifting the fraction in parallel during normalization of a floating point number.
It is yet another feature of the present invention to provide an apparatus, and method for implementing the apparatus, for achieving floating point normalization in a shorter time period than previously obtained, through the selective reduction in the number of machine cycles required to provide a normalized floating point result.